In a general nonvolatile memory, for preventing the resistance of a reference magnetic tunneling junction (Reference MTJ) from being far different from that of a cell magnetic tunneling junction (Cell MTJ) due to the floating factors in the fabrication process, the Reference MTJ is usually disposed between two Cell MTJ arrays. When the memory reads data by using a sense amplifier (SA), it compares the data from the Cell MTJ to the Reference MTJ to read the data that is stored in the Cell MTJ.
Please refer to FIG. 1, which illustrates a conventional load-balanced apparatus of memory. In this apparatus, there are two switches, MrefH and MrefL, connected to a reference input terminal (Ref) of the sense amplifier 11 and connected to a high state reference line and a low state reference line for providing a reference voltage or a reference current. A Cell input terminal connects to M switches connected to M bit-lines respectively. Take M=64 for example, there are 32 folds difference of the loading between the two input terminals, Ref and Cell, of the Sense Amplifier 11. Because of the difference of the charge and discharge time between the two input terminals, Ref and Cell, of the sense amplifier 11, the reading speed will be slower and there might exist mistakes in the data reading.
Please refer to FIG. 2, which illustrates another conventional load-balanced apparatus of memory disclosed in the U.S. Pat. No. 6,711,068 of Motorola. The memory interconnect structure has a top portion of bit lines that are labeled with a “T” designator from T0 to, for example, T31, and a bottom portion of bit lines that are labeled with a “B” designator, such as from B0 to B31, that are interfaced by a multiplexer in the form of a multiplexing switch module 232. Column decoder 220 has an N-channel transistor 234 having a source connected to a bit line (BL) conductor BLT0. An N-channel transistor 235 has a source connected to a bit line conductor BLT1. An N-channel transistor 236 has a source connected to a bit line conductor BLT15.
A left portion of the column decoder 222 (BL) generally has a plurality of transistors, such as a transistor 238, a transistor 239 and a transistor 240 and other intervening transistors (not shown).
An N-channel transistor 244 has a source connected to a reference voltage terminal for receiving a first “High Reference” voltage. A gate of transistor 244 is connected to a control signal labeled “TRE” meaning “Top Reference Enable”. Transistor 244 has a drain connected to conductor 241. A drain of an N-channel transistor 246 is connected to conductor 237. A gate of transistor 246 is connected to a control signal labeled “BRE” meaning “Bottom Reference Enable”, and a source of transistor 246 is connected to a reference voltage terminal for receiving a second “High Reference” voltage. An N-channel transistor 264 has a source connected to a reference voltage terminal for receiving a first “Low Reference” voltage. A gate of transistor 264 is connected to a control signal labeled “TRE” meaning “Top Reference Enable”. Transistor 264 has a drain connected to a conductor 263 that is a second data line of column decoder 222.
Multiplexing switch module 232 generally has balanced groups of N-channel transistors 272, 274, 276, 278, N-channel transistors 282, 284, N-channel transistors 286, 288 and N-channel transistors 292, 294, 296, 298.
In operation, each of the bit lines BLT0-BLT15, BLT16-BLT31, BLB0-BLB15 and BLB16-BLB31 is connected to a predetermined memory sub-array column (not shown). Assume for exemplary purposes only that transistor 235 is made conductive. In response, data from the accessed column is placed onto the sensing rail, conductor 237. In addition, the control signal TRE to the high reference in the top left sub-array and to the low reference in the top right sub-array is made active. In response, the data from the high reference bit line and the low reference bit line is placed onto the sensing rails of conductor 241 and conductor 263, respectively. Since only one sub-array is active, either the top or the bottom sub-array, none of the other switches formed by transistors 238, 239 through 240 that share the same conductor 241 is conductive. Also, none of the switches formed by transistors 260, 261 through 262 that share the same conductor 263 is conductive. Given that the number of switches connected to conductors 237, 241, 251 and 263 is equal, there is balanced capacitance on the interconnect structure. In particular, the capacitive loading on the accessed bit line connected to conductor 237 resulting from the off-state switches (transistors 234, 236, etc.) on conductor 237 is completely balanced with the capacitive loading on the high reference bit line connected to conductor 241 and the low reference bit line connected to conductor 63. Thus the capacitive loading for any enabled reference bit line is provided by the nonconductive transistor switches of the inactive sub-array connected to the common sensing rail that the enabled reference bit line is on.
The three inputs of sense amplifier 224 and conductors 270, 280 and 290 have an equal number, four, of switch junctions on them and thus maintain capacitive balance with respect to each other. The loading from transistors 272, 274, 276 and 278 is balanced by the loading from transistors 282, 284, 286 and 288 and is also balanced by the loading from transistors 292, 294, 296 and 298. Since there is complete balance within the structure of the four sensing rails of column decode 220 and column decode 222, and complete balance within the structure of the multiplexing switch module 232, data from any bit line and its corresponding pair of references (high and low) can all three be transported to the sense amplifier 224 in a fully balanced manner.
Based on the above, it is shown that the mentioned patent separates the memory device into four memory sub-arrays and connects each sub-array to a high or low reference cell switch by using switches. The mentioned patent reads the memory by using a sense amplifier with three input terminals, thereby making the loads of the three input terminals of the sense amplifier equal to the loads of the memory sub-arrays plus the load of a reference cell switch, so as to balance the load of each input terminal of the sense amplifier. However, the apparatus in the mentioned patent has to separate the memory into four memory sub-arrays and the operation thereof is more complicated.
Please refer to FIG. 3, which illustrates a further conventional load-balanced apparatus of memory disclosed in the U.S. Pat. No. 6,269,040 of IBM. This apparatus comprises two sub-arrays 342, 344 of memory cell columns, two switch units 341, 343 associated with the two sub-arrays 342, 344, respectively, two sense amplifiers 346, 348 for sensing data from the two sub-arrays 342, 344 via the two switch units 341, 343, respectively, and two connection units 345, 347 for providing electrical connections between input lines of the two sense amplifiers 346, 348. Each sub-array includes multiple memory cell columns and two reference cell columns which are preferably positioned in the middle of the multiple memory cell columns. For example, the first sub-array 342 has multiple memory cell columns CLA, CLB, CLC, CLD and two reference cell columns CL0, CL1, which are preferably placed in the middle of the memory cell columns CLA, CLB, CLC, CLD. Each memory cell column has multiple memory cells each having data “1” or “0” (i.e., higher or lower resistance). Reference cell column CLi has multiple reference cells each having value “1” (i.e., higher resistance), and reference cell column CL0 has multiple reference cells each having value “0” (i.e., lower resistance).
The second sub-array 344 and the second switch unit 343 have the same configuration as the first sub-array 342 and the first switch unit 341, except for connections between reference switches in the second switch unit 343 and input lines of the second sense amplifier 348.
Under control of the decoding signal R1, the first connection unit 345 can be electrically connected so that a conduction path is formed via the first connection unit 345 between a selected reference cell of the reference cell column CL1 via the reference switch SW1 and a selected reference cell of the reference cell column CL′0 via the reference switch SW′0. Thereby, values “1” and “0” are summed to provide the reference (i.e., averaged value “½”) to complement inputs of the first and second sense amplifiers 346, 348. In a like manner, the second connection unit 347 in response to the decoding signal R2 may sum the values “0” and “1” provided from selected reference cells of the reference cell column CL0 and the reference cell column CL′1, respectively. Once such a conduction path is formed and the currents having logic values “0” and “1” are summed, the first and second sense amplifiers 346, 348 divide or share the summed current so that each sense amplifier receives averaged (i.e., mid-level “½”) current.
Based on the above, it is shown that the mentioned patent separates the memory into two sub-cell arrays, a left sub-cell array and a right one, and increases the number of the reference cells to two. The mentioned patent reads the memory by using two sense amplifiers, thereby making the load of each sense amplifier equal by using the middle switch, so as to balance the load of each input terminal of the sense amplifier. This apparatus needs two sense amplifiers in practice, and the middle switch makes the loads of the input terminals of the sense amplifier unbalanced.
From the above description, it is known that how to develop a load-balanced apparatus of memory has become a major problem waited to be solved. In order to overcome the drawbacks in the prior arts, an improved load-balanced apparatus of memory is provided. The particular design in the present invention not only solves the problems described above, but also is easy to be implemented. Thus, the invention has the utility for the industry.